1. Field of the Invention
The present invention relates to a semiconductor memory with virtual ground array (VGA) system developed for the aim of reducing chip area in which, for example, a common connection of the sources and a common connection of the drains of memory cells are used as bit lines, and the source or the drain is shared by adjacent memory cells to reduce the number of drain contacts or source contacts and to greatly reduce the chip area. Specifically, the present invention relates to a semiconductor memory or the like in which stabilized reading is realized in such a manner that when a characteristic used as a reference in a differential readout determination operation is obtained from a memory cell (reference cell) of a memory cell array, variation in the characteristic is suppressed.
2. Description of the Prior Art
Since the VGA structure can adopt a memory array structure having extremely good area efficiency, the VGA structure is used as a way to realize a large capacity memory (for example, see FIG. 1 of the specification of United States Laid-Open Patent Publication No. 2005/0088878). Here, in order to reduce leakage of cell current into a neighbor cell (hereinafter referred to as neighbor effect) in sense operation caused by a common connection of the drains and a common connection of the sources, a technique is adopted which involves applying a voltage to the source of the neighbor cell in a source side sense operation (FIG. 5B in the specification of United States Laid-Open Patent Publication No. 2005/0088878). Also in a drain side sense operation, a technique is also adopted in which a voltage being the same as the drain voltage of the relevant cell is applied to the drain of the neighbor cell (see FIG. 2 of Japanese Laid-Open Patent Publication No. 2003-22684).
The above-mentioned VGA structure can be adopted not only to a main area which stores data, but also to a memory cell (reference cell) from which the characteristic used as a reference in the differential readout determination operation is obtained.
However, it is found that when the conventional VGA structure is used to form such a reference cell as mentioned above, a leakage current via a cell neighboring the reference cell varies in processes, which makes it difficult to realize stable reading.
FIG. 24 shows an algorism for reprogramming and readout operations of a conventional nonvolatile semiconductor memory. When a characteristic used as a reference is obtained from a memory cell (reference cell), programming of the reference cell is first performed in Step 1 such that the reference cell conducts a predetermined reference current. Then, in the reprogramming operation in actual use of the nonvolatile semiconductor memory, an erase operation in Step 2, a programming operation in Step 3, and a readout operation in Step 4 are performed on a main area.
FIG. 23 is a block diagram illustrating the conventional nonvolatile semiconductor memory.
With reference to FIG. 23, the programming of the reference cell in Step 1 will be first explained. A row decoder 3 selects a word line RWL1 to select a reference cell RC12 in a memory cell region 1 in which memories are arranged in an array. In this state, a column decoder 4 drives column selection lines CSp1 and CSp0 to have a logical value of 1, which allows application of voltages V1=Vd and V2=VSS generated in a programming bias circuit 9 respectively to main bit liens RMBL3 and RMBL2 via column selection transistors Cp1 and Cp0. At the same time, selection line driving circuits 2-2 and 2-1 drive block selection lines SEL6 and SEL2 to have a logical value of 1, which allows application of the Vd and the VSS respectively to subbit lines DBL3 and DBL2 via block selection transistors SL12 and SL02. Then, the Vd and the VSS are respectively applied to the source and the drain of the reference cell RC12, and electrons are injected in a charge accumulation region at a subbit line DBL3 side by a hot electron injection method, so that the reference cell is programmed.
Next, the readout operation performed in Step 2, Step 3, and Step 4 using the reference cell will be explained. Likewise, the row decoder 3 selects the word line RWL1 to select the reference cell RC12. In this state, the column decoder 4 drives column selection lines CSr1 and CSr0 to have a logical value of 1, which allows application of a voltage V3=Vb generated in a read bias circuit 7 to the main bit line RMBL2 via a column selection transistor Cr1, and connection of the main bit line RMBL3 to a reference side input of a sense amplifier 6 via a column selection transistor Cr0. At the same time, a column selection line CSn is driven to have a logical value of 1, which allows injection of a current Iadd from a neighbor effect suppression circuit 8 into a bit line RMBL0 via a column selection transistor Cn. At the same time, the selection line driving circuits 2-1 and 2-2 drive the block selection lines SEL2, SEL6, and SEL1 to have a logical value of 1, which allows application of the Vb to the subbit line DBL2 via the block selection transistor SL02, connection of the subbit line DBL3 to the sense amplifier 6 via the block selection transistor SL12, and injection of the current Iadd from the neighbor effect suppression circuit 8 into a subbit line DBL4 via a block selection transistor SL01. In this case, the current Iadd is set to have the same value as that of a leakage current Ines via a neighbor cell RC13 connected to the word line RWL1 which is connected to the reference cell RC12, so that the leakage current via the neighbor cell RC13 does not occur, and thus a cell current Iref of the reference cell RC12 is faithfully input into the sense amplifier 6. That is, the above-mentioned function of the neighbor effect suppression circuit 8 reduces the neighbor effect, which is particular to the VGA structure. Then, as shown in FIG. 25, based on a result from an integration of currents input from a main side and from a reference side, a difference potential between both nodes is differentially determined and the readout operation is performed.
Since in the conventional structure, characteristics of cells, including the neighbor cell RC13 but excepting the reference cell RC12, vary in processes, it is not in all cases possible to completely counterbalance variation in leakage current Ines by the current Iadd. Therefore, reference side input current input to the sense amplifier 6 varies, and a reference side input voltage SA_IN_Ref of the sense amplifier 6 varies in the range of SA_IN_Ref− to SA_IN_Ref+ as shown in the graph in FIG. 25, which disables a stable readout operation.
Explanations have been given with reference to a system in which a cell current is taken at a source side (source sense system). However, in a system in which a cell current is taken at a drain side (drain sense system), a neighbor cell RC11 has similar influence.